SystemVerilog 3.1a Language Reference Manual - UAH Electrical and

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SystemVerilog 3.1a Language Reference Manual Accellera’s Extensions to Verilog® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description…
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SystemVerilog 3.1a Language Reference Manual Accellera’s Extensions to Verilog® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models Copyright © 2002, 2003, 2004 by Accellera Organization, Inc. 1370 Trancas Street #163 Napa, CA 94558 Phone: (707) 251-9977 Fax: (707) 251-9877 All rights reserved. No part of this document may be reproduced or distributed in any medium what- soever to any third parties without prior written consent of Accellera Organization, Inc. SystemVerilog 3.1a (5/13/04) SystemVerilog 3.1a Language Reference Manual Accellera’s Extensions to Verilog® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models Accellera SystemVerilog 3.1a Extensions to Verilog-2001 ii Copyright 2004 Accellera. All rights reserved . Verilog is a registered trademark of Cadence Design Systems, San Jose, CA Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. iii STATEMENT OF USE OF ACCELLERA STANDARDS Accellera Standards documents are developed within Accellera and the Technical Committees of Accellera Organization, Inc. Accellera develops its standards through a consensus development process, approved by its members and board of directors, which brings together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are not necessarily members of Accellera and serve without compensa- tion. While Accellera administers the process and establishes rules to promote fairness in the consensus devel- opment process, Accellera does not independently evaluate, test, or verify the accuracy of any of the information contained in its standards. Use of an Accellera Standard is wholly voluntary. Accellera disclaims liability for any personal injury, prop- erty or other damage, of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or indirectly resulting from the publication, use of, or reliance upon this, or any other Accellera Stan- dard document. Accellera does not warrant or represent the accuracy or content of the material contained herein, and expressly disclaims any express or implied warranty, including any implied warranty of merchantability or suitability for a specific purpose, or that the use of the material contained herein is free from patent infringement. Accellera Standards documents are supplied “AS IS”. The existence of an Accellera Standard does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of an Accellera Standard. Further- more, the viewpoint expressed at the time a standard is approved and issued is subject to change due to devel- opments in the state of the art and comments received from users of the standard. Every Accellera Standard is subjected to review periodically for revision and update. Users are cautioned to check to determine that they have the latest edition of any Accellera Standard. In publishing and making this document available, Accellera is not suggesting or rendering professional or other services for, or on behalf of, any person or entity. Nor is Accellera undertaking to perform any duty owed by any other person or entity to another. Any person utilizing this, and any other Accellera Standards docu- ment, should rely upon the advice of a competent professional in determining the exercise of reasonable care in any given circumstances. Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to specific applications. When the need for interpretations is brought to the attention of Accellera, Accellera will initiate action to prepare appropriate responses. Since Accellera Standards represent a consensus of con- cerned interests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason, Accellera and the members of its Technical Committees are not able to provide an instant response to interpretation requests except in those cases where the matter has previously received for- mal consideration. Comments for revision of Accellera Standards are welcome from any interested party, regardless of member- ship affiliation with Accellera. Suggestions for changes in documents should be in the form of a proposed change of text, together with appropriate supporting comments. Comments on standards and requests for inter- pretations should be addressed to: Accellera Organization 1370 Trancas Street #163 Napa, CA 94558 USA Accellera SystemVerilog 3.1a Extensions to Verilog-2001 iv Copyright 2004 Accellera. All rights reserved . Accellera is the sole entity that may authorize the use of Accellera-owned certification marks and/or trade- marks to indicate compliance with the materials set forth herein. Authorization to photocopy portions of any individual standard for internal or personal use must be granted by Accellera Organization, Inc., provided that permission is obtained from and any required fee is paid to Accel- lera. To arrange for authorization please contact Lynn Horobin, Accellera, 1370 Trancas Street #163, Napa, CA 94558, phone (707) 251-9977, e-mail lynn@accellera.org. Permission to photocopy portions of any indi- vidual standard for educational classroom use can also be obtained from Accellera. Note: Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. Accellera shall not be responsible for identifying patents for which a license may be required by an Accellera standard or for conducting inquir- ies into the legal validity or scope of those patents that are brought to its attention. Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. v Acknowledgements This SystemVerilog Language Reference Manual was developed by experts from many different fields, includ- ing design and verification engineers, Electronic Design Automation (EDA) companies, EDA vendors, and members of the IEEE 1364 Verilog standard working group. The SystemVerilog Language Reference Manual (LRM) was specified by the Accellera SystemVerilog com- mittee. Four subcommittees worked on various aspects of the SystemVerilog 3.1 specification: — The Basic/Design Committee (SV-BC) worked on errata and extensions to the design features of System- Verilog 3.1. — The Enhancement Committee (SV-EC) worked on errata and extensions to the testbench features of Sys- temVerilog 3.1. — The Assertions Committee (SV-AC) worked on errata and extensions to the assertion features of System- Verilog 3.1. — The C Application Programming Interface (API) Committee (SV-CC) worked on errata and extensions to the Direct Programming Interface (DPI), the assertions and coverage APIs and the VPI features of System- Verilog 3.1. The committee chairs were: Vassilios Gerousis, SystemVerilog 3.1 and 3.1a Committee General Chair Basic/Design Committee Johny Srouji, SystemVerilog 3.1 and 3.1a Chair Karen Pieper, SystemVerilog 3.1 and 3.1a Co-Chair Enhancement Committee David Smith, SystemVerilog 3.1 and 3.1a Chair Stefen Boyd, SystemVerilog 3.1 Co-Chair Neil Korpusik, SystemVerilog 3.1a Co-Chair Assertions Committee Faisal Haque, SystemVerilog 3.1 and 3.1a Chair Steve Meier, SystemVerilog 3.1 Co-Chair Arif Samad, SystemVerilog 3.1a Co-Chair C API Committee Swapnajit Mittra, SystemVerilog 3.1 and 3.1a Chair Ghassan Khoory, SystemVerilog 3.1 and 3.1a Co-Chair Stuart Sutherland, SystemVerilog 3.1 and 3.1a Language Reference Manual Editor Stefen Boyd, SystemVerilog 3.1 BNF Annex. Editor Brad Pierce, SystemVerilog 3.1a BNF Annex Editor Accellera SystemVerilog 3.1a Extensions to Verilog-2001 vi Copyright 2004 Accellera. All rights reserved . Committee members included (listed alphabetically by last name) * indicates this person was also an active member of the IEEE 1364 Verilog Standard Working Group + indicates this person was actively involved in SystemVerilog 3.1 ++ indicates this person was actively involved in SystemVerilog 3.1a +++ indicates this person was actively involved in SystemVerilog 3.1 and 3.1a SystemVerilog 3.1/3.1a Basic/Design Committee SystemVerilog 3.1/3.1a Enhancement Committee SystemVerilog 3.1/3.1a Assertions Committee SystemVerilog 3.1/3.1a C API Committee Kevin Cameron+ Cliff Cummings*+++ Dan Jacobi+++ Jay Lawrence+++ Mark Hartoog++ Peter Flake++ Matt Maidment+++ Francoise Martinolle*+++ Rishiyur Nikhil++ Karen Pieper*+++ Brad Pierce+++ David Rich+++ Steven Sharp*+ Johny Srouji+++ Gord Vreugdenhil*+ Doug Warmke++ Stefen Boyd*+ Dennis Brophy+++ Michael Burns+++ Kevin Cameron+ Cliff Cummings*+++ Peter Flake+ Jeff Freedman+ Neil Korpusik+++ Jay Lawrence+++ Francoise Martinolle*+ Don Mills+ Mehdi Mohtashemi+++ Phil Moorby+ Karen Pieper*+ Brad Pierce+++ Dave Rich++ Ray Ryan++ Arturo Salz+++ David Smith+++ Stuart Sutherland*+++ Roy Armoni+++ Surrendra Dudani+++ Cindy Eisner+ Harry Foster+ Faisal Haque+++ John Havlicek+++ Richard Ho+ Adam Krolnik*+++ David Lacey+ Joseph Lu+++ Erich Marschner+ Steve Meier+ Hillel Miller++ Prakash Narain+ Koushik Roy++ Arif Samad++ Andrew Seawright+ Bassam Tabbara+++ John Amouroux+++ Kevin Cameron+++ Ralph Duncan++ Charles Dawson++ João Geada+++ Ghassan Khoory+++ Andrzej Litwiniuk+++ Avinash Mani++ Francoise Martinole*+++ Swapnajit Mittra+++ Michael Rohleder+++ John Stickley+++ Stuart Swan+++ Bassam Tabbara+++ Kurt Takara+ Doug Warmke+++ Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. vii Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section 2 Literal Values.................................................................................................................................. 4 2.1 Introduction (informative) ...............................................................................................................4 2.2 Literal value syntax..........................................................................................................................4 2.3 Integer and logic literals ..................................................................................................................4 2.4 Real literals ......................................................................................................................................5 2.5 Time literals .....................................................................................................................................5 2.6 String literals....................................................................................................................................5 2.7 Array literals ....................................................................................................................................6 2.8 Structure literals ...............................................................................................................................6 Section 3 Data Types....................................................................................................................................... 8 3.1 Introduction (informative) ...............................................................................................................8 3.2 Data type syntax...............................................................................................................................9 3.3 Integer data types ...........................................................................................................................10 3.4 Real and shortreal data types .........................................................................................................11 3.5 Void data type ................................................................................................................................11 3.6 chandle data type ...........................................................................................................................11 3.7 String data type ..............................................................................................................................12 3.8 Event data type...............................................................................................................................16 3.9 User-defined types .........................................................................................................................16 3.10 Enumerations .................................................................................................................................17 3.11 Structures and unions.....................................................................................................................22 3.12 Class...............................................................................................................................................26 3.13 Singular and aggregate types .........................................................................................................27 3.14 Casting ...........................................................................................................................................27 3.15 $cast dynamic casting ....................................................................................................................28 3.16 Bit-stream casting ..........................................................................................................................29 Section 4 Arrays ............................................................................................................................................ 32 4.1 Introduction (informative) .............................................................................................................32 4.2 Packed and unpacked arrays ..........................................................................................................32 4.3 Multiple dimensions ......................................................................................................................33 4.4 Indexing and slicing of arrays........................................................................................................34 4.5 Array querying functions ...............................................................................................................35 4.6 Dynamic arrays ..............................................................................................................................35 4.7 Array assignment ...........................................................................................................................37 4.8 Arrays as arguments.......................................................................................................................38 4.9 Associative arrays ..........................................................................................................................39 4.10 Associative array methods .............................................................................................................41 4.11 Associative array assignment.........................................................................................................44 4.12 Associative array arguments ..........................................................................................................44 4.13 Associative array literals................................................................................................................44 4.14 Queues ...........................................................................................................................................45 4.15 Array manipulation methods .........................................................................................................47 Section 5 Data Declarations ......................................................................................................................... 52 5.1 Introduction (informative) .............................................................................................................52 5.2 Data declaration syntax..................................................................................................................52 5.3 Constants........................................................................................................................................52 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 viii Copyright 2004 Accellera. All rights reserved . 5.4 Variables ........................................................................................................................................53 5.5 Scope and lifetime .........................................................................................................................54 5.6 Nets, regs, and logic.......................................................................................................................55 5.7 Signal aliasing................................................................................................................................56 5.8 Type compatibility .........................................................................................................................58 Section 6 Attributes....................................................................................................................................... 61 6.1 Introduction (informative) .............................................................................................................61 6.2 Default attribute type .....................................................................................................................61 Section 7 Operators and Expressions.......................................................................................................... 62 7.1 Introduction (informative) .............................................................................................................62 7.2 Operator syntax..............................................................................................................................62 7.3 Assignment operators ....................................................................................................................62 7.4 Operations on logic and bit types ..................................................................................................63 7.5 Wild equality and wild inequality..................................................................................................63 7.6 Real operators ................................................................................................................................64 7.7 Size.................................................................................................................................................64 7.8 Sign ................................................................................................................................................64 7.9 Operator precedence and associativity ..........................................................................................64 7.10 Built-in methods ............................................................................................................................65 7.11 Static Prefixes .............................................................................................................................
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